Abstract:
We use rigorous physics-based analysis of transistors scaled to 5nm design rules and beyond, considering several flavors of FinFETs and nanowires with Si and non-Si channels. The transistors are placed into a representative standard library cell for Power-Performance-Area (PPA) analysis. The PPA analysis reveals that Middle-Of-Line (MOL) RC dominates circuit behavior at 5nm design rules. Optimization of the energy-delay trade-off points towards continuing the ongoing fin depopulation trend and possible transition from FinFETs to nanowires. Besides, innovative approaches to building library cells provide simultaneous improvements in energy consumption and in routability of the short library cells. These observations point to the rising role of random variability in determining chip area and cost. We perform comparative analysis of major variability mechanisms and their implications on PPA outcome for different technologies, ranging from 130nm to 2nm design rules.