Abstract:
To pave the way for mass deployment of IoT, the semiconductor industry must deliver higher bandwidth and lower cost packaging solutions. Recent times have seen successful volume production for 2.5D package portfolios, applied within GPU systems, placed side-by-side with 3D IC stacked memory on Si interposer. At the same time, fan out technology has great potential to bring the promise of wafer level packaging to the mainstream within a broad set of applications. During his presentation, CP will discuss and demonstrate how these two technologies are highly complementary and together they will launch a new era of wafer level packaging for SiP. He’ll also elaborate on what this innovation means for the industry on the road ahead.