Abstract:
The continued shrink of integrated circuits according to Moore’s law has led to an era where the gains in device performance are now limited by the performance of the interconnects. Numerous challenges emerge as the interconnect dimension continues to shrink. Void free metallization and RC delay degradation are among the key risks to interconnect scaling and warrant in-depth investigations. Materials and process integration innovations are critical to address the emerging challenges. Multiple approaches to address above-mentioned BEOL challenges will be reviewed in this presentation.
With the adoption of self-aligned multiple patterning and unidirectional routing, via resistance becomes more critical in the future technology nodes. High resistivity barrier/liner is the dominant factor in modulating via resistance. A novel metallization scheme is being developed where the via are filled selectively using a bottom-up electroless deposition; the overlying interconnect then may use conventional Cu metallization. This novel via pre-fill approach not only enables lower via resistance, but also augments the process window for void-free metallization of the overlying trench features. Our recent via pre-fill process integration results demonstrate the via resistance benefits along with parametric yields comparable to the conventional baseline metallization scheme.
Rapid rise of Cu resistance with shrinking interconnect dimension is identified as the critical bottleneck on BEOL performance. Loss of conducting metal cross section to barrier/liner and higher Cu resistivity are the two main factors that lead to high Cu interconnect resistance. To address these two challenges, a novel metal with a short electronic mean free path, high melting point, and requiring a thinner barrier/liner is being investigated as the alternative metallization candidate. We will present our progress on the investigation of the fundamental material properties understanding, void-free filling, and process integration.
Material innovation has been critical to the semiconductor technology. Multiple new materials have been introduced into semiconductor fabrication during the evolution of the technology. With interconnect in the critical path, development of novel solutions would provide an alternative path to the bottleneck in scaling to enable practical realization of gains in overall circuit performance.