Abstract:
In the Semiconductor Industry, use of processor cores in analog devices continues to increase. For the analog test engineer, this presents a question of what to do with the core during production test. CPU-BIST is a methodology currently used in many TI devices to test individual IP blocks. But even with CPU-BIST, the core is mostly idle at test. In this paper, a novel solution of concurrent firmware based testing was created for a mixed-signal production test solution which utilizes the DUT core and the ATE together to enable increased levels of testing. Processor test firmware was written to manage the unknown time interactions when testing multiple IP blocks at a time. The test firmware, working together with the similarly structured ATE program, was used to reduce the overall test time by 6% and improve the yield by 1.5% with no decrease in test coverage. Test time for impacted IP blocks was reduced by ~38%. Also, implementation of this methodology identified design opportunities for increasing concurrent firmware based testing in the next generation device. The results show that embedded processor cores in analog devices can be used to achieve reduced test time and same/increased test coverage versus traditional test time reduction methods. This translates to a reduced test cost and improved yield. For the analog test engineer who has an embedded processor, this is a significant addition of a new tool to the test development / test cost reduction tool box.